As is well known by those skilled in the art, a continuing goal in manufacturing and production of semiconductors is a reduction in size of components and circuits with the concurrent result of an increase in the number of circuits and/or circuit elements on a single semiconductor device. This relentless and successful reduction in size of the circuit elements has also required reduction in the size of the conductive lines connecting devices and circuits. However, as the conducting lines are designed to be smaller and smaller, the resistance of the interconnects increases. Further, as the number of dielectric layers increases, the capacitive coupling between lines on the same level and adjacent level increases.
In the past, aluminum was used as the metal interconnect lines and silicon oxide as the dielectric. However, newer manufacturing techniques now favor copper as the metal for interconnect lines and various low K materials (organic and inorganic) are favored as the dielectric material. Not surprisingly, these material changes have required changes in the processing methods. In particular, because of the difficulty of etching copper without also causing unacceptable damage to the dielectric material, the technique of forming the metal interconnect lines has experienced significant changes. Namely, whereas aluminum interconnects could be formed by depositing a layer of aluminum and then using photoresist, lithography, and etching to leave a desired pattern of aluminum lines, the formation of copper interconnect lines are typically formed by a process now commonly referred to as a Damascene process. The Damascene process is almost the reverse of etching, and simply stated a trench, canal or via is cut, etched or otherwise formed in the underlying dielectric and is then filled with metal (i.e., copper). The metal deposited outside the trenches and vias is then polished away.
The process is rather straightforward if lines of metallization or copper layer were to be formed at only one level. However, as is well known by those skilled in the art, semiconductor devices are now formed at multiple levels on a chip and consequently metallization or interconnects, which are on the order of 100 nm (nanometers) and less, must also be formed at each level. Further, not only are multiple levels of metallization required, but these multiple levels must be interconnected. The difficulty in connecting vias through the dielectric (which will then be filled with copper) that will align with a 100 nm interconnect line at another level in the same semiconductor device is obvious.
However, for the manufacture of some semiconductor devices such as TJ (Tunnel Junctions) elements, there are still other problems that must be solved. For example, the planarization in open areas adjacent densely packed TJ elements often result in significant “dishing” problems. More specifically, TJ planarization required during the manufacture of MRAM (Magnetic Random Access Memory) elements poses special difficulties, since the height of these densely packed TJ elements is substantially less than a typical via height. Therefore the resulting structures are more prone to interlevel shorts than a normal dual damascence metal level and require stringent pattern factor rules if the fill structures are made of the same kind of magnetic elements used for the active TJ elements. These stringent rules have been found to be necessary to avoid active TJ's being shorted by lines of metallization, and also to avoid shorts between the metal lines above and below the TJ's. These fill structures provide an unreliable electrical path between both metal levels and have to be carefully placed to avoid unwanted electrical connections. Therefore, although the stringent form factor rules solve the problem of shorting active TJ's, the use of these rules puts severe limits on the design of wiring levels and often results in ineffective wiring and wasted silicon “floor space.”